Інструкції процесорів AVR

Нижче в табличній формі приведений набір команд процесорів AVR, детальніший опис їх можна знайти в AVR Data Book.

Асемблер не розрізняє регістр символів. Операнди можуть бути таких видів:

Rd: Результуючий (і початковий) регістр в регістровому файлі.

Rr: Початковий регістр в регістровому файлі.

b: Константа (3 біта), може бути константний вираз.

s: Константа (3 біта), може бути константний вираз.

P: Константа (5-6 біт), може бути константний вираз.

K6: Константа (6 біт), може бути константний вираз.

K8: Константа (8 біт), може бути константний вираз.

k: Константа (р-р залежить від інструкції), або константний вираз.

q: Константа (6 біт), може бути константний вираз.

Rdl: R24, R26, R28, R30. Для інструкцій ADIW і SBIW.

X,Y,Z: Регістри непрямої адресації (X=R27:R26, Y=R29:R28, Z=R31:R30)

Mnemonic	Operands	Description	Operation	Flags	# Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD	Rd, Rr	Add Two Registers	Rd ← Rd + Rr	Z,C,N,V,H
ADC	Rd, Rr	Add with Carry Two Registers	Rd ← Rd + Rr + C	Z,C,N,V,H
ADIW	Rdl, K	Add Immediate to Word	Rdh:Rdl ← Rdh:Rdl + K	Z,C,N,V,S
SUB	Rd, Rr	Subtract Two Registers	Rd ← Rd - Rr	Z,C,N,V,H
SUBI	Rd, K	Subtract Constant from Registers	Rd ← Rd - K	Z,C,N,V,H
SBC	Rd, Rr	Subtract with Carry Two Registers	Rd ← Rd - Rr - C	Z,C,N,V,H
SBCI	Rd, K	Subtract with Carry Constant from Reg.	Rd ← Rd - K - C	Z,C,N,V,H
SBIW	Rd, K	Subtract Immediate from Word	Rdh:Rdl ← Rdh:Rdl - K	Z,C,N,V,S
AND	Rd, Rr	Logical AND Registers	Rd ← Rd∙Rr	Z,N,V
ANDI	Rd, K	Logical AND Register and Constant	Rd ← Rd∙K	Z,N,V
OR	Rd, Rr	Logical OR Registers	Rd ← Rd v Rr	Z,N,V
ORI	Rd, K	Logical OR Register and Constant	Rd ← Rd v K	Z,N,V
EOR	Rd, Rr	Exclusive OR Registers	Rd ← Rd + Rr	Z,N,V
COM	Rd	One's Complement	Rd ← $FF - Rd	Z,C,N,V
NEG	Rd	Two's Complement	Rd ← $00 - Rd	Z,C,N,V,H
SBR	Rd, K	Set Bit(s) in Register	Rd ← Rd v K	Z,N,V
CBR	Rd, K	Clear Bit(s) in Register	Rd ← Rd ∙ ($FF - K)	Z,N,V
INC	Rd	Increment	Rd ← Rd + 1	Z,N,V
DEC	Rd	Decrement	Rd ← Rd - 1	Z,N,V
TST	Rd	Test for Zero or Minus	Rd ← Rd∙Rd	Z,N,V
CLR	Rd	Clear Register	Rd ← Rd + Rd	Z,N,V
SER	Rd	Set Register	Rd ← $FF	None

Mnemonic	Operands	Description	Operation	Flags	# Clocks
BRANCH INSTRUCTIONS
RJMP	k	Relative Jump	PC ← PC + k + 1	None
IJMP		Indirect Jump to (Z)	PC ← Z	None
RCALL	k	Relative Subroutine Call	PC ← PC + k + 1	None
ICALL		Indirect Call to (Z)	PC ← Z	None
RET		Subroutine Return	PC ← STACK	None
RETI		Interrupt Return	PC ← STACK	I
CPSE	Rd, Rr	Compare, Skip if Equal	if (Rd = Rr) PC ← PC + 2 or 3	None	1/2/3.
CP	Rd, Rr	Compare	Rd - Rr	Z,N,V,C,H
CPC	Rd, Rr	Compare with Carry	Rd - Rr - C	Z,N,V,C,H
CPI	Rd, K	Compare Register with Immediate	Rd - K	Z,N,V,C,H
SBRC	Rr, b	Skip if Bit in Register Cleared	if (Rr(b) = 0) PC ← PC + 2 or 3	None	1/2/3.
SBRS	Rr, b	Skip if Bit in Register is Set	if (Rr(b) = 1) PC ← PC + 2 or 3	None	1/2/3.
SBIC	P, b	Skip if Bit in I/O Register Cleared	if (P(b) = 0) PC ← PC + 2 or 3	None	1/2/3.
SBIS	P, b	Skip if Bit in I/O Register is Set	if (P(b) = 1) PC ← PC + 2 or 3	None	1/2/3.
BRBS	s, k	Branch if Status Flag Set	if (SREG(s) = 1) then PC ← PC + k + 1	None	1/2.
BRBC	s, k	Branch if Status Flag Cleared	if (SREG(s) = 0) then PC ← PC + k + 1	None	1/2.
BREQ	k	Branch if Equal	if (Z = 1) then PC ← PC + k + 1	None	1/2.
BRNE	k	Branch if Not Equal	if (Z = 0) then PC ← PC + k + 1	None	1/2.
BRCS	k	Branch if Carry Set	if (C = 1) then PC ← PC + k + 1	None	1/2.
BRCC	k	Branch if Carry Cleared	if (C = 0) then PC ← PC + k + 1	None	1/2.
BRSH	k	Branch if Same or Higher	if (C = 0) then PC ← PC + k + 1	None	1/2.
BRLO	k	Branch if Lower	if (C = 1) then PC ← PC + k + 1	None	1/2.
BRMI	k	Branch if Minus	if (N = 1) then PC ← PC + k + 1	None	1/2.
BRPL	k	Branch if Plus	if (N = 0) then PC ← PC + k + 1	None	1/2.
BRGE	k	Branch if Greater or Equal, Signed	if (N + V = 0) then PC ← PC + k + 1	None	1/2.
BRLT	k	Branch if Less Than Zero, Signed	if (N + V = 1) then PC ← PC + k + 1	None	1/2.
BRTS	k	Branch if T-flag Set	if (T = 1) then PC ← PC + k + 1	None	1/2.
BRTC	k	Branch if T-flag Cleared	if (T = 0) then PC ← PC + k + 1	None	1/2.
BRVS	k	Branch if Overflow Flag is Set	if (V = 1) then PC ← PC + k + 1	None	1/2.
BRVC	k	Branch if Overflow Flag is Cleared	if (V = 0) then PC ← PC + k + 1	None	1/2.
BRIE	k	Branch if Interrupt Enabled	if (I = 1) then PC ← PC + k + 1	None	1/2.
BRID	k	Branch if Interrupt Disabled	if (I = 0) then PC ← PC + k + 1	None	1/2.
Mnemonic	Operands	Description	Operation	Flags	# Clocks
DATA TRANSFER INSTRUCTIONS
MOV	Rd, Rr	Move between Registers	Rd ← Rr	None
LDI	Rd, K	Load Immediate	Rd ← K	None
LD	Rd, X	Load Indirect	Rd ← (X)	None
LD	Rd, X+	Load Indirect and Post-inc.	Rd ← (X), X ← X + 1	None
LD	Rd, -X	Load Indirect and Pre-dec.	X ← X-1, Rd ← (X)	None
LD	Rd, Y	Load Indirect	Rd ← (Y)	None
LD	Rd, Y+	Load Indirect and Post-inc.	Rd ← (Y), Y ← Y + 1	None
LD	Rd, -Y	Load Indirect and Pre-dec.	Y ← Y - 1, Rd ← (Y)	None
LDD	Rd, Y+q	Load Indirect with Displacement	Rd ← (Y + q)	None
LD	Rd, Z	Load Indirect	Rd ← (Z)	None
LD	Rd, Z+	Load Indirect and Post-inc.	Rd ← (Z), Z ← Z + 1	None
LD	Rd, -Z	Load Indirect and Pre-dec.	Z ← Z - 1, Rd ← (Z)	None
LDD	Rd, Z+q	Load Indirect with Displacement	Rd ← (Z + q)	None
LDS	Rd, k	Load Direct from SRAM	Rd ← (k)	None
ST	X, Rr	Store Indirect	(X) ← Rr	None
ST	X+, Rr	Store Indirect and Post-inc.	(X) ← Rr, X ← X + 1	None
ST	-X, Rr	Store Indirect and Pre-dec.	X ← X - 1, (X) ← Rr	None
ST	Y, Rr	Store Indirect	(Y) ← Rr	None
ST	Y+, Rr	Store Indirect and Post-inc.	(Y) ← Rr, Y ← Y + 1	None
ST	-Y, Rr	Store Indirect and Pre-dec.	Y ← Y - 1, (Y) ← Rr	None
STD	Y+q, Rr	Store Indirect with Deplacement	(Y + q) ← Rr	None
ST	Z, Rr	Store Indirect	(Z) ← Rr	None
ST	Z+, Rr	Store Indirect and Post-inc.	(Z) ← Rr, Z ← Z + 1	None
ST	-Z, Rr	Store Indirect and Pre-dec.	Z ← Z - 1, (Z) ← Rr	None
STD	Z+q, Rr	Store Indirect with Deplacement	(Z + q) ← Rr	None
STS	k, Rr	Store Direct to SRAM	(k) ← Rr	None
LPM		Load Program Memory	R0 ← (Z)	None
IN	Rd, P	In Port	Rd ← P	None
OUT	P, Rr	Out Port	P ← Rr	None
PUSH	Rr	Push Register on Stack	STACK ← Rr	None
POP	Rd	Push Register from Stack	Rd ← STACK	None

Mnemonic	Operands	Description	Operation	Flags	# Clocks
BIT AND BIT-TEST INSTUCTIONS
SBI	P,b	Set Bit in I/O Register	I/O(P,b) ← 1	None
CBI	P,b	Clear Bit in I/O Register	I/O(P,b) ← 0	None
LSL	Rd	Logical Shift Left	Rd(n + 1) ← Rd(n), Rd(0) ← 0	Z,C,N,V
LSR	Rd	Logical Shift Right	Rd(n) ← Rd(n + 1), Rd(7) ← 0	Z,C,N,V
ROL	Rd	Rotate Left through Carry	Rd(0) ← C, Rd(n + 1) ← Rd(n),C ← Rd(7)	Z,C,N,V
ROR	Rd	Rotate Right through Carry	Rd(7) ← C, Rd(n) ← Rd(n + 1),C ← Rd(0)	Z,C,N,V
ASR	Rd	Arithmetic Shift Right	Rd(n) ← Rd(n + 1), n = 0..6	Z,C,N,V
SWAP	Rd	Swap Nibbles	Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)	None
BSET	s	Flag Set	SREG (s) ← 1	SREG(s)
BCLR	s	Flag Clear	SREG (s) ← 0	SREG(s)
BST	Rr, b	Bit Store from Register to T	T ← Rr(b)	T
BLD	Rd, b	Bit Load from T to Register	Rr(b) ← T	None
SEC		Set Carry	C ← 1	C
CLC		Clear Carry	C ← 0	C
SEN		Set Negative Flag	N ← 1	N
CLN		Clear Negative Flag	N ← 0	N
SEZ		Set Zero Flag	Z ← 1	Z
CLZ		Clear Zero Flag	Z ← 0	Z
SEI		Global Interrupt Enable	I ← 1	I
CLI		Global Interrupt Disable	I ← 0	I
SES		Set Signed Test Flag	S ← 1	S
CLS		Clear Signed Test Flag	S ← 0	S
SEV		Set Two's Complement Overflow	V ← 1	V
CLV		Clear Two's Complement Overflow	V ← 0	V
SET		Set T in SREG	T ← 1	T
CLT		Clear T in SREG	T ← 0	T
SHE		Set Half-carry Flag in SREG	H ← 1	H
CLH		Clear Half-carry Flag in SREG	H ← 0	H
NOP		No Operation		None
SLEEP		Sleep	(see specific descr. for Sleep function)	None
WDR		Watchdog Reset	(see specific descr. for WDR/timer)	None

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