Instruction Length

Crafting an ISA

•We‘ll look at some of the decisions facing an instruction set architecture, and

•how those decisions were made in the design of the MIPS instruction set.

•MIPS, like SPARC, PowerPC, and Alpha AXP, is a RISC (Reduced Instruction Set Computer) ISA.

–fixed instruction length

–few instruction formats

–load/store architecture

•RISC architectures worked because they enabled pipelining. They continue to thrive because they enable parallelism.

•Variable-length instructions (Intel 80x86, VAX) require multi-step fetch and decode, but allow for a much more flexible and compact instruction set.

•Fixed-length instructions allow easy fetch and decode, and simplify pipelining and parallelism.

All MIPS instructions are 32 bits long.

Accessing the Operands

•operands are generally in one of two places:

–registers (32 int, 32 fp)

–memory (232locations)

•registers are

–easy to specify

–close to the processor (fast access)

•the idea that we want to access registers whenever possible led to load-store architectures.

–normal arithmetic instructions only access registers

–only access memory with explicit loads and stores.

Load-store architectures can do:

add r1=r2+r3

and

load r3, M(address)

⇒forces heavy dependence on registers, which is exactly what you want in today‘s CPUs can‘t do

add r1 = r2 + M(address)

-more instructions

+ fast implementation (e.g., easy pipelining)

How Many Operands

•Most instructions have three operands (e.g., z = x + y).

•Well-known ISAsspecify 0-3 (explicit) operands per instruction.

•Operands can be specified implicitly or explicity.

Читайте також:

<== попередня сторінка	\|	наступна сторінка ==>
The Instruction Set Architecture	\|	Four principles of IS architecture

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