The “Single Cycle” ALU

Completing ALU Design

Adding the Instruction Fetch Circuit

Fig. 3.12 Architecture with the Instruction Fetch Circuit

Fig. 3.13 The designed ALU circuit

NOTE: Design is complete except for jump instruction path.

In this “ALU design” all the processing hardware necessary to implement the instruction set are used. Note that we have NOT considered the control circuits (that tell the ALU what to do), and will cover those later.

This basic processor design is referred to as the “single cycle ALU” (or sometimes the “single cycle CPU”).

The reason is that this CPU is designed so that ANY instruction can be processed in one cycle of the CPU clock.

Lets consider how this “single cycle” CPU works.

Since the ALU is basically combinational logic, the “tick” of the clock governs ALU register behavior, which times the process.

A single clock cycle is from rising to rising or falling to falling edge of the clock. Let us use falling to falling as the reference (remember: a master-slave ff’s output changes on the falling edge of the clock).

Consider what happens when the clock “ticks.”

– The PC is already updated.

– The instruction at memory location [PC] is retrieved. [PC] → [PC+4]

– Instruction is decoded/registers are identified (operands).

– Register output buses send data into ALU; ALU function is identified.

– Register data “flows through” the ALU and is processed.

(stores store )

– In loads/stores, data memory is accessed for load or store.)

– The memory or ALU results are stored back in a register, if necessary.

<== попередня сторінка	\|	наступна сторінка ==>
Data Buses and ALU Register/Register Functions	\|	Single Cycle Timing

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