Single Cycle Timing
1. (Start of cycle) Instruction retrieved into instruction register.
2 (PC contents updated.)
3. Instruction decoded and registers accessed.
4. Register contents gated onto ALU input bus (immediate operands sign-extended and input to ALU).
5. ALU function identified and ALU result obtained.
6. ALU results used to access memory location if required.
7. Memory data written (store) or retrieved (load) if memory access instruction.
8. Data gated onto register input bus.
9. (End of cycle) Instruction result stored in designated register if required.
Fig. 3.13 Single Cycle Timing Architecture
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- The “Single Cycle” ALU
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