The Memory of the Modern Supercomputers

The organization of computer memory has received much attention over the years. There are two general ways of partitioning memory, which can be called vertical and horizontal. The incentive for structuring memory in a vertical or hierarchical manner is that fast memories cost more per bit than slower ones. Moreover, the larger the memory is, the longer it takes to access items that have been stored randomly. The processing units in most large computers communicate directly with a small, very fast memory of perhaps several hundred words. Data can be transferred to or from one of these disk units at a maximum rate of half a million words per second, and in practice it is possible to maintain data flow between central memory and several disk units simultaneously.

The maximum rate of transfer of information to or from a memory device is known as a bandwidth. In order for the average computing speed not to be dominated by the smaller bandwidth of the lower memory levels, programs must be arranged so that as much computation as possible is done with instruction and data at the higher levels before the need arises to reload the higher level from the one below. This is an important consideration in programming vector operations for supercomputers, whose central-memory bandwidth is small in relation to the megaflop rate that can be sustained for data held in the register set.

Several multiprocessing supercomputers currently under development incorporate a number of independent parallel memory modules that linked to an equal number of independent processors through a high-speed program-controlled switch so that all the memories are equally accessible to all the processors. For pipelines processors still another kind of horizontal partitioning of central memory has been devised: the memory is divided into a number of "phased" memory banks, so described because they operate with their access cycles out of phase with one another. The rationale for the scheme is that random-access central memories are relatively slow, requiring the passage of a certain minimum number of clock periods between successive memory references. In order to keep vector operands streaming at a rate of one word per clock period to feed a pipeline, vectors are stored with consecutive operands in different banks. The phase shift that "opens" successively referenced banks is equal to one processor clock period.

The memory of the modern supercomputers – is organized hierarchically. The two register memories are the smallest, followed in capacity by central memory, extended semiconductor memory and disk memory. The extended semiconductor memory has just begun to appear in supercomputer installations because rotating-disc technology has not kept pace with the increasing speed of processors.

All the functional units can run concurrently, but not all can run at top speed concurrently because they share common resources, such as data paths 01 memory access cycles. Moreover, conditional branches in the program interrupt the smooth flow of instructions through the instruction processor. Before the processor issues an instruction, it must wait until it is clear that all the resources needed for the execution of the instruction will be available when they are needed.

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